1. Field of the Invention
The present invention relates to methods of testing an integrated circuit. In particular, the present invention relates to methods of testing memory elements in an integrated circuit.
2. Discussion of the Related Art
In an integrated circuit, it is advantageous for a memory element, such as a static random access memory (SRAM) device, to retain its stored data during a momentary dip in power supply voltage. The "V.sub.dr " (data retention voltage) test is devised to test such data retention capability. Under the V.sub.dr test, data is first written into the memory element. Then, the power supply voltage (V.sub.cc) is lowered momentarily (e.g. for one second) to a value below that voltage at which data is written into the memory element (e.g., 0.6 volts), before returning the power supply voltage to the normal operating supply voltage (e.g. 4 volts). The memory element is then read to determine if the stored data is retained.
However, there are two mechanisms by which a memory element may lose its stored data. These mechanisms are illustrated by FIG. 1. FIG. 1 shows, in the prior art, an SRAM cell 100 sharing a power supply bus 109 with a logic circuit 150. As shown in FIG. 1, an SRAM cell 100 includes load devices 101 and 102, N-type transistors 107 and 108, and transfer transistors 103 and 104. Transfer transistors 103 and 104, which are part of a "word line", are controlled by the same control signal A at their respective gate terminals 107 and 108. Load devices 101 and 102 can be MOS transistors, thin-film transistors, or polysilicon resistors. During a read access, the control signal A is asserted at terminals 107 and 108 of transfer transistors 103 and 104 to allow the datum stored in SRAM cell 100 be read as complementary signals B and B at terminals 106 and 105 respectively. During a write access, control signal A is asserted at terminals 107 and 108 of transfer transistors 103 and 104 to allow the datum represented by the complementary signals B and B at terminals 106 and 105, respectively, to be stored into SRAM cell 100. As shown in FIG. 1, SRAM cell 100 and logic circuit 150 receive a common power supply voltage from power supply bus 109. In addition, control signal A is an output signal of logic circuit 150.
During the V.sub.dr test, SRAM cell 100 may lose its stored data if the low power supply voltage at power supply bus 109 causes the voltages of terminals 110 and 111 to fall below the requisite gate-to-source voltage necessary to turn on either one of transistors 107 and 108. Alternatively, the data in SRAM cell 100 may also be over-written if the low supply voltage causes unintended switching in logic circuit 150, such that control signal A is unintentionally asserted, resulting in an unintended write operation into SRAM cell 100. This unintended write operation may be triggered, for example, because logic circuit 150 is designed to operate only at the limited supply voltage range of 4-6 volts and some portions of logic circuit 150 are designed to have a "trip-point", i.e. the threshold value between logic states, above V.sub.dr. For example, depending on both the inductance and the current in supply voltage bus 109 (i.e. V.sub.cc) overshooting or undershooting during signal transmission can result in memory content loss. Hence, in the prior art, a V.sub.dr test in a central processing unit (CPU) that requires lowering the supply voltage below 1.5 volts, is virtually impossible because of the likelihood that false signal transitions, such as those discussed above, can trigger unintended write operations which affect data in the memory cells. The momentary dip in power supply voltage under the V.sub.dr test can lead to not only data corruption, but also masking of a true data retention problem. Such masking occurs when the data lost is replaced correctly, albeit fortuitously, by an unintended write operation of the type discussed above.